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[Other resource] Verilog_ASystem(ADS2006A)

Description: Using Verilog-A in Advanced Design System，英文版的关于Verilog_A的相关介绍。
Platform: | Size: 189535 | Author: 李白洋 | Hits:

[Other resource] 发一个基于ModelSim仿真的Verilog源代码包

Description: 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
Platform: | Size: 74902 | Author: 阿乐 | Hits:

[Other resource] Verilog 语法速查手册

Description: Verilog 语法速查手册，做成了一个页面形式，方便Verilog开发人员查询！-Verilog Grammar Check manual, it would be a one page form to facilitate the development of Verilog staff inquiries!
Platform: | Size: 24907 | Author: 飞扬 | Hits:

[Other resource] verilog实现ALU的源代码

Description: verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
Platform: | Size: 1382 | Author: 飞扬 | Hits:

[Other resource] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 250084 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] VHDL的基本数学运算库

Description: VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
Platform: | Size: 232448 | Author: | Hits:

[VHDL-FPGA-Verilog] 一篇用VHDL实现快速傅立叶变换的论文

Description: 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat
Platform: | Size: 62464 | Author: | Hits:

[Windows Develop] DES算法讲解

Description: 一个很好的DES讲解-a good on DES
Platform: | Size: 301056 | Author: 杜涛 | Hits:

[Windows Develop] ram

Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
Platform: | Size: 1024 | Author: 杨艳 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_5_10

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 4096 | Author: 丁谨 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_8_23

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 6144 | Author: 丁谨 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_11_52

Description: verilog浮点乘发器，特定数据结构，指数底为10-Verilog float by their hair, a specific data structure, the index for the end of 10
Platform: | Size: 23552 | Author: 丁谨 | Hits:

[Embeded-SCM Develop] echo_dj

Description: verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time.
Platform: | Size: 4096 | Author: 丁谨 | Hits:

[Embeded-SCM Develop] tlc2543

Description: 12位串行A/D转换芯片TLC2543的驱动程序--Driver program for 12-bit serial A/D conversion chip TLC2543.
Platform: | Size: 1024 | Author: 李罗 | Hits:

[Windows Develop] 有译zhup

Description: 交通灯控制电路 一、 设计任务与要求 1．设计一个十字路口的交通灯控制电路，要求甲车道和乙车道两条交叉道路上的车辆交替 运行，每次通行时间都设为25秒； 2．要求黄灯先亮5秒，才能变换运行车道； 3．黄灯亮时，要求每秒钟闪亮一次 。 二、实验预习要求 1．复习数字系统设计基础。 2．复习多路数据选择器、二进制同步计数器的工作原理。 3．根据交通灯控制系统框图，画出完整的电路图。-a control circuit design tasks and requirements 1. Design a crossroads of traffic lights control circuit, and requested a B lane cross-road of two lanes of traffic on the turn of operation, each time prevailing Set 25 seconds; 2. Asked yellow first-five seconds, can transform running lanes; 3. Bright yellow light, flashing a request per second. Two experimental rehearsal requirements 1. Review of digital systems design basis. 2. Review of Multiple Choice of data, binary synchronous counter to the principle. 3. According to the traffic light control system block diagram to depict the integrity of the circuit.
Platform: | Size: 1024 | Author: 刘鹏 | Hits:

[Embeded-SCM Develop] verilog_book

Description: 通向ip设计的必看的一本书籍--A good book for IP design.
Platform: | Size: 1849344 | Author: 王惠 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ethernet_verilog

Description: 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
Platform: | Size: 78848 | Author: 张念华 | Hits:

[Embeded-SCM Develop] lzma

Description: lzma的压缩算法再嵌入式系统上的实现，lzma是一个对bin类型文件压缩比很高的压缩算法，一般压缩后的文件大小是原理的1/3-LZMA compression algorithm embedded system again on the realization LZMA was a bin file types high compression ratio of compression algorithm, the general compressed file size is the principle of 1/3
Platform: | Size: 7168 | Author: 木头 | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog编写的alu模块-Verilog modules prepared by the ALU
Platform: | Size: 1024 | Author: 刘陆陆 | Hits:

[VHDL-FPGA-Verilog] pn_code

Description: 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures
Platform: | Size: 35840 | Author: 高广鹤 | Hits:
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